Code Design for Dependable Systems : Theory and Practical Applications
Eiji. Fujiwara
Bok Engelsk 2006 · Electronic books.
| Annen tittel | |
|---|---|
| Utgitt | Hoboken : : Wiley, , 2006.
|
| Omfang | 1 online resource (718 p.)
|
| Opplysninger | Description based upon print version of record.. - Code Design for Dependable Systems; Contents; Preface; 1 Introduction; 1.1 Faults and Failures; 1.2 Error Models; 1.3 Error Recovery Techniques for Dependable Systems; 1.4 Code Design Process for Dependable Systems; References; 2 Mathematical Background and Matrix Codes; 2.1 Introduction to Algebra; 2.2 Linear Codes; 2.3 Basic Matrix Codes; Exercises; References; 3 Code Design Techniques for Matrix Codes; 3.1 Minimum-Weight & Equal-Weight-Row Codes; 3.2 Odd-Weight-Column Codes; 3.3 Even-Weight-Row Codes; 3.4 Odd-Weight-Row Codes; 3.5 Rotational Codes; Exercises; References. - 11 Codes for Mass Memories. - 4 Codes for High-Speed Memories I: Bit Error Control Codes4.1 Modified Hamming SEC-DED Codes; 4.2 Modified Double-Bit Error Correcting BCH Codes; 4.3 On-Chip ECCs; Exercises; References; 5 Codes for High-Speed Memories II: Byte Error Control Codes; 5.1 Single-Byte Error Correcting (SbEC) Codes; 5.2 Single-Byte Error Correcting and Double-Byte Error Detecting (SbEC-DbED) Codes; 5.3 Single-Byte Error Correcting and Single p-Byte within a Block Error Detecting (SbEC-S(p×b/B)ED) Codes; Exercises; References; 6 Codes for High-Speed Memories III: Bit / Byte Error Control Codes. - 6.1 Single-Byte / Burst Error Detecting SEC-DED Codes6.2 Single-Byte Error Correcting and Double-Bit Error Detecting (SbEC-DED) Codes; 6.3 Single-Byte Error Correcting and Double-Bit Error Correcting (SbEC-DEC) Codes; 6.4 Single-Byte Error Correcting and Single-Byte Plus Single-Bit Error Detecting (SbEC-(Sb + S)ED) Codes; Exercises; References; 7 Codes for High-Speed Memories IV: Spotty Byte Error Control Codes; 7.1 Spotty Byte Errors; 7.2 Single Spotty Byte Error Correcting (S(t/b)EC) Codes; 7.3 Single Spotty Byte Error Correcting and Single-Byte Error Detecting (S(t/b)EC-SbED) Codes. - 7.4 Single Spotty Byte Error Correcting and Double Spotty Byte Error Detecting (S(t/b)EC-D(t/b)ED) Codes7.5 A General Class of Spotty Byte Error Control Codes; Exercises; References; 8 Parallel Decoding Burst / Byte Error Control Codes; 8.1 Parallel Decoding Burst Error Control Codes; 8.2 Parallel Decoding Cyclic Burst Error Correcting Codes; 8.3 Transient Behavior of Parallel Encoder / Decoder Circuits of Error Control Codes; Exercises; References; 9 Codes for Error Location: Error Locating Codes; 9.1 Error Location of Faulty Packages and Faulty Chips. - 9.2 Block Error Locating (S(b/p×b)EL) Codes9.3 Single-Bit Error Correcting and Single-Block Error Locating (SEC-S(b/p×b)EL) Codes; 9.4 Single-Bit Error Correcting and Single-Byte Error Locating (SEC-S(e/b)EL) Codes; 9.5 Burst Error Locating Codes; 9.6 Code Conditions for Error Locating Codes; Exercises; References; 10 Codes for Unequal Error Control / Protection ( UEC / UEP ); 10.1 Error Models for UEC Codes and UEP Codes; 10.2 Fixed-Byte Error Control UEC Codes; 10.3 Burst Error Control UEC / UEP Codes; 10.4 Application of the UEC / UEP Codes; Exercises; References. - Theoretical and practical tools to master matrix code design strategy and techniqueError correcting and detecting codes are essential to improving system reliability and have popularly been applied to computer systems and communication systems. Coding theory has been studied mainly using the code generator polynomials; hence, the codes are sometimes called polynomial codes. On the other hand, the codes designed by parity check matrices are referred to in this book as matrix codes. This timely book focuses on the design theory for matrix codes and their practical applications for th
|
| Emner | |
| Sjanger | |
| Dewey | |
| ISBN | 0471756180. - 9780471756187
|
