VHDL : Coding and Logic Synthesis with Synopsys
Weng Fook. Lee
Bok Engelsk 2000 · Electronic books.
| Utgitt | Burlington : : Elsevier Science, , 2000.
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| Omfang | 1 online resource (417 p.)
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| Opplysninger | Description based upon print version of record.. - Front Cover; VHDL: Coding and Logic Synthesis with Synopsys®; Copyright Page; Table of Contents; List of Figures; List of Tables; List of Examples; Preface; Acknowledgment; Trademarks; Part I: VHDL CODING; Chapter 1. Introduction; 1.1 Conventional Design-Schematic Capture; 1.2 Hardware Description Language; 1.3 VHDL Design Structure; 1.4 Component Instantiation Within a VHDL Design Structure; 1.5 Structural, Behavioral, and Synthesizable VHDL Design Structure; 1.6 Usage of Library Declarations in VHDL Design Structure; Chapter 2. VHDL Simulation and Synthesis Flow. - Chapter 13. Synthesis Links to Layout13.1 Forward-Annotation; 13.2 Wireload Models; 13.3 Floorplanning a Design; 13.4 Post Layout Optimization; Chapter 14. Design Guideline to Follow for Efficient Synthesis; Appendix A. (STD_LOGIC_1164 Library); Appendix B. (Shifter Synthesis Results); Appendix C. (Counter Synthesis Results); Appendix D. (Pipeline Microcontroller Synthesis Results-Top-Down Compilation); Appendix E. (EDIF File of Synthesized Microcontroller Example from Chapter 6); Appendix F. (SDF File from Synthesized Microcontroller Example of Chapter 6); Glossary; Bibliography; Index. - Chapter 3. Synthesizable Code for Basic Logic Components3.1 AND Logic; 3.2 OR Logic; 3.3 NOT Logic; 3.4 NAND Logic; 3.5 NOR Logic; 3.6 Tristate Buffer Logic; 3.7 Complex Logic Gate; 3.8 Latch; 3.9 Flip-Flop; 3.10 Decoder; 3.11 Encoder; 3.12 Multiplexer; 3.13 Priority Encoder; 3.14 Memory Cell; 3.15 Adder; 3.16 Component Inference; Chapter 4. SignaI Versus Variable; 4.1 Variable; 4.2 Signal; 4.3 When to Use Signal and When to Use Variable; 4.4 Usage of Loopback Signal; Chapter 5. Examples of Complex Synthesizable Code; 5.1 Shifter; 5.2 Counter; 5.3 Memory Module; 5.4 Car Traffic Controller. - Chapter 6. Pipeline Microcontroller Synthesizable Design6.1 Instruction Set Definition; 6.2 Architectural Definition; 6.3 Pipeline Definition; 6.4 Microarchitecture Definition for the Pipeline Microcontroller; Part II: LOGIC SYNTHESIS WITH SYNOPSYS; Chapter 7. Timing Considerations in Design; 7.1 Setup Timing Violation; 7.2 Hold Timing Violation; 7.3 Setup/Hold Timing Considerations in Synthesis; 7.4 Microarchitectural Tweaks for Fixing Setup Time Violations; 7.5 Microarchitectural Tweaks for Fixing Hold Time Violations; 7.6 Asynchronous/False Paths; 7.7 Multicycle Paths. - Chapter 8. VHDL Synthesis with Timing Constraints8.1 Introduction to Design Compiler; 8.2 Using Design Compiler for Synthesis; 8.3 Performance Tweaks; 8.4 Area Optimization in Synthesis Tweaks; 8.5 Fixing Hold-Time Violations in Synopsys; 8.6 Misc Synthesis Commands Generally Used; 8.7 Top-Down and Bottoms-Up Compilation; Chapter 9. GTECH Instantiation; Chapter 10. DesignWare Library; 10.1 Creating Your Own DesignWare Library; Chapter 11. Testability Issues in Synthesis; 11.1 Multiplexed Flip-Flop Scan Style; 11.2 Using Synopsys Test Compiler for Scan Insertion; Chapter 12. FPGA Synthesis. - This book provides the most up-to-date coverage using the Synopsys program in the design of integrated circuits. The incorporation of ""synthesis tools"" is the most popular new method of designing integrated circuits for higher speeds covering smaller surface areas.Synopsys is the dominant computer-aided circuit design program in the world. All of the major circuit manufacturers and ASIC design firms use Synopsys. In addition, Synopsys is used in teaching and laboratories at over 600 universities.* First practical guide to using synthesis with S
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| Emner | |
| Sjanger | |
| Dewey | |
| ISBN | 0124406513
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