CMOS IC Layout : Concepts, Methodologies, and Tools
Dan. Clein
Bok Engelsk 1999 · Electronic books.
| Utgitt | Burlington : : Elsevier Science, , 1999.
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| Omfang | 1 online resource (287 p.)
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| Opplysninger | Description based upon print version of record.. - Cover; CONTENTS; Preface; Acknowledgments; CHAPTER 1. INTRODUCTION; 1.1 History of the Profession; 1.2 What Is Layout Design?; 1.3 IC Design Flow; CHAPTER 2. SCHEMATIC FUNDAMENTALS; 2.1 The MOS Transistor: The Basic Circuit Structure; 2.2 Logic Gates; 2.3 Transmission Gates; 2.4 Understanding the Schematic Connectivity; 2.5 Review of Fundamental Electrical Laws; CHAPTER 3. LAYOUT DESIGN; 3.1 Introduction to CMOS VLSI Manufacturing Processes; 3.2 Layers and Connectivity; 3.3 Introduction to Transistor Layout; 3.4 Process Design Rules; 3.5 Vertical Connection Diagram. - 3.6 A General Procedure to Follow3.7 Preparing to Start; 3.8 General Guidelines; 3.9 Implementing the Design; 3.10 Verification; 3.11 Final Steps; CHAPTER 4. LAYOUT DESIGN FLOWS; 4.1 What Is a Flow?; 4.2 Microprocessor Design Flow; 4.3 ASSPs; 4.4 Memories; 4.5 System on a Chip, or SOC; 4.6 CAD Tools as Part of a Flow; CHAPTER 5. ADVANCED TECHNIQUES FOR SPECIALIZED BUILDING-BLOCK LAYOUT DESIGN; 5.1 Standard Cell Libraries; 5.2 Special Logic Cells; 5.3 Pad Cells; 5.4 Memory Design Leaf Cells; 5.5 Laser Fuse Cells; 5.6 Chip Finishing Cells. - 9.1 Layout of Circuits Designed for Change9.2 Planning for Unknown Changes; 9.3 Engineering Change Orders; 9.4 Guidelines for Proper Layout; CHAPTER 10. COMPUTER-AIDED DESIGN (CAD) TOOLS FOR LAYOUT; 10.1 Introduction; 10.2 Planning Tools; 10.3 Layout Generation Tools; 10.4 Support Tools; Appendices; Index; File Directory. - CHAPTER 6. ADVANCED TECHNIQUES FOR BUILDING-BLOCK INTERCONNECT LAYOUT DESIGN6.1 Power Grid; 6.2 Clock Signals; 6.3 Interconnect Routing; CHAPTER 7. LAYOUT DESIGN TECHNIQUES TO ADDRESS ELECTRICAL CHARACTERISTICS; 7.1 Resistance; 7.2 Capacitance; 7.3 Symmetry; 7.4 Special Electrical Requirements; CHAPTER 8. LAYOUT CONSIDERATIONS DUE TO PROCESS CONSTRAINTS; 8.1 Wide Metal Slits; 8.2 Large Metal via Implementations; 8.3 Step Coverage Rules; 8.4 Multiple Rule Sets; 8.5 Antenna Rules; 8.6 Special Design Rules; 8.7 Latch-Up; CHAPTER 9. LAYOUT DESIGN TECHNIQUES IN AN UNCERTAIN ENVIRONMENT. - This book includes basic methodologies, review of basic electrical rules and how they apply, design rules, IC planning, detailed checklists for design review, specific layout design flows, specialized block design, interconnect design, and also additional information on design limitations due to production requirements.*Practical, hands-on approach to CMOS layout theory and design*Offers engineers and technicians the training materials they need to stay current in circuit design technology.*Covers manufacturing processes and their effect on layout and design decisions
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| Emner | |
| Sjanger | |
| Dewey | |
| ISBN | 0750671947
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