Advanced FPGA Design : Architecture, Implementation, and Optimization
Steve. Kilts
Bok Engelsk 2007 · Electronic books.
| Annen tittel | |
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| Utgitt | Hoboken : : Wiley, , 2007.
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| Omfang | 1 online resource (354 p.)
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| Opplysninger | Description based upon print version of record.. - Advanced FPGA Design; Flowchart of Contents; Contents; Preface; Acknowledgments; 1. Architecting Speed; 1.1 High Throughput; 1.2 Low Latency; 1.3 Timing; 1.3.1 Add Register Layers; 1.3.2 Parallel Structures; 1.3.3 Flatten Logic Structures; 1.3.4 Register Balancing; 1.3.5 Reorder Paths; 1.4 Summary of Key Points; 2. Architecting Area; 2.1 Rolling Up the Pipeline; 2.2 Control-Based Logic Reuse; 2.3 Resource Sharing; 2.4 Impact of Reset on Area; 2.4.1 Resources Without Reset; 2.4.2 Resources Without Set; 2.4.3 Resources Without Asynchronous Reset; 2.4.4 Resetting RAM. - 10.1.1 Problems with Fully Asynchronous Resets10.1.2 Fully Synchronized Resets; 10.1.3 Asynchronous Assertion, Synchronous Deassertion; 10.2 Mixing Reset Types; 10.2.1 Nonresetable Flip-Flops; 10.2.2 Internally Generated Resets; 10.3 Multiple Clock Domains; 10.4 Summary of Key Points; 11. Advanced Simulation; 11.1 Testbench Architecture; 11.1.1 Testbench Components; 11.1.2 Testbench Flow; 11.1.2.1 Main Thread; 11.1.2.2 Clocks and Resets; 11.1.2.3 Test Cases; 11.2 System Stimulus; 11.2.1 MATLAB; 11.2.2 Bus-Functional Models; 11.3 Code Coverage; 11.4 Gate-Level Simulations; 11.5 Toggle Coverage. - 11.6 Run-Time Traps. - 2.4.5 Utilizing Set/Reset Flip-Flop Pins2.5 Summary of Key Points; 3. Architecting Power; 3.1 Clock Control; 3.1.1 Clock Skew; 3.1.2 Managing Skew; 3.2 Input Control; 3.3 Reducing the Voltage Supply; 3.4 Dual-Edge Triggered Flip-Flops; 3.5 Modifying Terminations; 3.6 Summary of Key Points; 4. Example Design: The Advanced Encryption Standard; 4.1 AES Architectures; 4.1.1 One Stage for Sub-bytes; 4.1.2 Zero Stages for Shift Rows; 4.1.3 Two Pipeline Stages for Mix-Column; 4.1.4 One Stage for Add Round Key; 4.1.5 Compact Architecture; 4.1.6 Partially Pipelined Architecture. - 4.1.7 Fully Pipelined Architecture4.2 Performance Versus Area; 4.3 Other Optimizations; 5. High-Level Design; 5.1 Abstract Design Techniques; 5.2 Graphical State Machines; 5.3 DSP Design; 5.4 Software/Hardware Codesign; 5.5 Summary of Key Points; 6. Clock Domains; 6.1 Crossing Clock Domains; 6.1.1 Metastability; 6.1.2 Solution 1: Phase Control; 6.1.3 Solution 2: Double Flopping; 6.1.4 Solution 3: FIFO Structure; 6.1.5 Partitioning Synchronizer Blocks; 6.2 Gated Clocks in ASIC Prototypes; 6.2.1 Clocks Module; 6.2.2 Gating Removal; 6.3 Summary of Key Points; 7. Example Design: I2S Versus SPDIF. - 7.1 I2S7.1.1 Protocol; 7.1.2 Hardware Architecture; 7.1.3 Analysis; 7.2 SPDIF; 7.2.1 Protocol; 7.2.2 Hardware Architecture; 7.2.3 Analysis; 8. Implementing Math Functions; 8.1 Hardware Division; 8.1.1 Multiply and Shift; 8.1.2 Iterative Division; 8.1.3 The Goldschmidt Method; 8.2 Taylor and Maclaurin Series Expansion; 8.3 The CORDIC Algorithm; 8.4 Summary of Key Points; 9. Example Design: Floating-Point Unit; 9.1 Floating-Point Formats; 9.2 Pipelined Architecture; 9.2.1 Verilog Implementation; 9.2.2 Resources and Performance; 10. Reset Circuits; 10.1 Asynchronous Versus Synchronous. - This book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGA's beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience.
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| Emner | |
| Sjanger | |
| Dewey | |
| ISBN | 9780470054376
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